1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus, and more particularly to apparatus and methods for generating a supply voltage in a semiconductor memory apparatus.
2. Related Art
As illustrated in FIG. 1, a conventional semiconductor memory apparatus includes a capacitor C to stabilize an internal circuit 1 and a supply voltage VCC applied to the internal circuit 1. When the supply voltage VCC becomes higher than a target level, the capacitor C stores heightened electric charges. Also, when the supply voltage VCC becomes lower than the target level, the capacitor C discharges the stored electric charges. In this manner, the level of the supply voltage VCC can be maintained at a constant level.
FIG. 2, however, is a diagram illustrating how noise that can effect the supply voltage VCC when the conventional semiconductor memory apparatus of FIG. 1 enters and exits from a power-down mode. For example, when a Dynamic Random Access Memory (DRAM) device enters a power-down mode, the power consumption of the DRAM device is rapidly reduced, which can cause a spike in the supply voltage VCC. Meanwhile, when the DRAM exits from the power-down mode, the power consumption of the DRAM device is rapidly increased, which can cause a dip in the supply voltage VCC.
Accordingly, when the DRAM device enters the power-down mode, the supply voltage VCC supplied to the internal circuit 1 becomes higher than the target level for a predetermined time. Meanwhile, when the DRAM exits from the power-down mode, the supply voltage VCC becomes lower than the target level for a predetermined time. Such supply voltage VCC instability is due to the small capacitance of the capacitor C provided to stabilize the supply voltage VCC.
Normal operation of the internal circuit 1 requires a stable supply voltage VCC at a target level. However, when the level of the supply voltage VCC is above or below the target level, i.e., the level of the supply voltage VCC is unstable, then normal operation of the internal circuit 1 cannot be achieved. For example, a Delay Locked Loop (DLL) circuit, in which the supply voltage VCC is provided for a DLL operation, cannot generate a normal DLL clock when the DLL operating voltage gets higher or lower than the target level. But this type of problem can effect any internal circuit that receive the supply voltage VCC buffered by the capacitor C.